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| 1 : | edgomez | 1.1 | ;/**************************************************************************** |
| 2 : | ; * | ||
| 3 : | ; * XVID MPEG-4 VIDEO CODEC | ||
| 4 : | ; * - CPUID check processors capabilities - | ||
| 5 : | ; * | ||
| 6 : | ; * Copyright (C) 2001 Michael Militzer <isibaar@xvid.org> | ||
| 7 : | ; * 2004 Andre Werthmann <wertmann@aei.mpg.de> | ||
| 8 : | ; * | ||
| 9 : | ; * This program is free software ; you can redistribute it and/or modify | ||
| 10 : | ; * it under the terms of the GNU General Public License as published by | ||
| 11 : | ; * the Free Software Foundation ; either version 2 of the License, or | ||
| 12 : | ; * (at your option) any later version. | ||
| 13 : | ; * | ||
| 14 : | ; * This program is distributed in the hope that it will be useful, | ||
| 15 : | ; * but WITHOUT ANY WARRANTY ; without even the implied warranty of | ||
| 16 : | ; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 : | ; * GNU General Public License for more details. | ||
| 18 : | ; * | ||
| 19 : | ; * You should have received a copy of the GNU General Public License | ||
| 20 : | ; * along with this program ; if not, write to the Free Software | ||
| 21 : | ; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 22 : | ; * | ||
| 23 : | ; * $Id$ | ||
| 24 : | ; * | ||
| 25 : | ; ***************************************************************************/ | ||
| 26 : | |||
| 27 : | BITS 64 | ||
| 28 : | |||
| 29 : | %macro cglobal 1 | ||
| 30 : | %ifdef PREFIX | ||
| 31 : | %ifdef MARK_FUNCS | ||
| 32 : | global _%1:function %1.endfunc-%1 | ||
| 33 : | %define %1 _%1:function %1.endfunc-%1 | ||
| 34 : | %else | ||
| 35 : | global _%1 | ||
| 36 : | %define %1 _%1 | ||
| 37 : | %endif | ||
| 38 : | %else | ||
| 39 : | %ifdef MARK_FUNCS | ||
| 40 : | global %1:function %1.endfunc-%1 | ||
| 41 : | %else | ||
| 42 : | global %1 | ||
| 43 : | %endif | ||
| 44 : | %endif | ||
| 45 : | %endmacro | ||
| 46 : | |||
| 47 : | ;============================================================================= | ||
| 48 : | ; Constants | ||
| 49 : | ;============================================================================= | ||
| 50 : | |||
| 51 : | %define CPUID_TSC 0x00000010 | ||
| 52 : | %define CPUID_MMX 0x00800000 | ||
| 53 : | %define CPUID_SSE 0x02000000 | ||
| 54 : | %define CPUID_SSE2 0x04000000 | ||
| 55 : | |||
| 56 : | %define EXT_CPUID_3DNOW 0x80000000 | ||
| 57 : | %define EXT_CPUID_AMD_3DNOWEXT 0x40000000 | ||
| 58 : | %define EXT_CPUID_AMD_MMXEXT 0x00400000 | ||
| 59 : | |||
| 60 : | ;;; NB: Make sure these defines match the ones defined in xvid.h | ||
| 61 : | %define XVID_CPU_MMX (1<< 0) | ||
| 62 : | %define XVID_CPU_MMXEXT (1<< 1) | ||
| 63 : | %define XVID_CPU_SSE (1<< 2) | ||
| 64 : | %define XVID_CPU_SSE2 (1<< 3) | ||
| 65 : | %define XVID_CPU_3DNOW (1<< 4) | ||
| 66 : | %define XVID_CPU_3DNOWEXT (1<< 5) | ||
| 67 : | %define XVID_CPU_TSC (1<< 6) | ||
| 68 : | |||
| 69 : | ;============================================================================= | ||
| 70 : | ; Read only data | ||
| 71 : | ;============================================================================= | ||
| 72 : | |||
| 73 : | ALIGN 64 | ||
| 74 : | %ifdef FORMAT_COFF | ||
| 75 : | SECTION .rodata | ||
| 76 : | %else | ||
| 77 : | SECTION .rodata align=16 | ||
| 78 : | %endif | ||
| 79 : | |||
| 80 : | vendorAMD: | ||
| 81 : | db "AuthenticAMD" | ||
| 82 : | |||
| 83 : | ;============================================================================= | ||
| 84 : | ; Macros | ||
| 85 : | ;============================================================================= | ||
| 86 : | |||
| 87 : | %macro CHECK_FEATURE 3 | ||
| 88 : | mov rcx, %1 | ||
| 89 : | and rcx, rdx | ||
| 90 : | neg rcx | ||
| 91 : | sbb rcx, rcx | ||
| 92 : | and rcx, %2 | ||
| 93 : | or %3, rcx | ||
| 94 : | %endmacro | ||
| 95 : | |||
| 96 : | ;============================================================================= | ||
| 97 : | ; Code | ||
| 98 : | ;============================================================================= | ||
| 99 : | |||
| 100 : | SECTION .text align=16 | ||
| 101 : | |||
| 102 : | ; int check_cpu_feature(void) | ||
| 103 : | ; NB: | ||
| 104 : | ; in theory we know x86_64 CPUs support mmx, mmxext, sse, sse2 but | ||
| 105 : | ; for security sake, when intel cpus will come with amd64 support | ||
| 106 : | ; it will be necessary to check if 3dnow can be used or not... | ||
| 107 : | ; so better use cpuid, even if it's mostly ignored for now. | ||
| 108 : | |||
| 109 : | cglobal check_cpu_features | ||
| 110 : | check_cpu_features: | ||
| 111 : | |||
| 112 : | push rbx | ||
| 113 : | push rbp | ||
| 114 : | |||
| 115 : | sub rsp, 12 ; Stack space for vendor name | ||
| 116 : | |||
| 117 : | xor rbp, rbp | ||
| 118 : | |||
| 119 : | ; get vendor string, used later | ||
| 120 : | xor rax, rax | ||
| 121 : | cpuid | ||
| 122 : | mov [rsp], ebx ; vendor string | ||
| 123 : | mov [rsp+4], edx | ||
| 124 : | mov [rsp+8], ecx | ||
| 125 : | test rax, rax | ||
| 126 : | |||
| 127 : | jz near .cpu_quit | ||
| 128 : | |||
| 129 : | ; NB: we don't test for cpuid support like in ia32, we know | ||
| 130 : | ; it is supported. | ||
| 131 : | mov rax, 1 | ||
| 132 : | cpuid | ||
| 133 : | |||
| 134 : | ; RDTSC command ? | ||
| 135 : | CHECK_FEATURE CPUID_TSC, XVID_CPU_TSC, rbp | ||
| 136 : | |||
| 137 : | ; MMX support ? | ||
| 138 : | CHECK_FEATURE CPUID_MMX, XVID_CPU_MMX, rbp | ||
| 139 : | |||
| 140 : | ; SSE support ? | ||
| 141 : | CHECK_FEATURE CPUID_SSE, (XVID_CPU_MMXEXT|XVID_CPU_SSE), rbp | ||
| 142 : | |||
| 143 : | ; SSE2 support? | ||
| 144 : | CHECK_FEATURE CPUID_SSE2, XVID_CPU_SSE2, rbp | ||
| 145 : | |||
| 146 : | ; extended functions? | ||
| 147 : | mov rax, 0x80000000 | ||
| 148 : | cpuid | ||
| 149 : | cmp rax, 0x80000000 | ||
| 150 : | jbe near .cpu_quit | ||
| 151 : | |||
| 152 : | mov rax, 0x80000001 | ||
| 153 : | cpuid | ||
| 154 : | |||
| 155 : | ; AMD cpu ? | ||
| 156 : | lea rsi, [vendorAMD wrt rip] | ||
| 157 : | lea rdi, [rsp] | ||
| 158 : | mov rcx, 12 | ||
| 159 : | cld | ||
| 160 : | repe cmpsb | ||
| 161 : | jnz .cpu_quit | ||
| 162 : | |||
| 163 : | ; 3DNow! support ? | ||
| 164 : | CHECK_FEATURE EXT_CPUID_3DNOW, XVID_CPU_3DNOW, rbp | ||
| 165 : | |||
| 166 : | ; 3DNOW extended ? | ||
| 167 : | CHECK_FEATURE EXT_CPUID_AMD_3DNOWEXT, XVID_CPU_3DNOWEXT, rbp | ||
| 168 : | |||
| 169 : | ; extended MMX ? | ||
| 170 : | CHECK_FEATURE EXT_CPUID_AMD_MMXEXT, XVID_CPU_MMXEXT, rbp | ||
| 171 : | |||
| 172 : | .cpu_quit: | ||
| 173 : | |||
| 174 : | mov rax, rbp | ||
| 175 : | |||
| 176 : | add rsp, 12 | ||
| 177 : | |||
| 178 : | pop rbp | ||
| 179 : | pop rbx | ||
| 180 : | |||
| 181 : | ret | ||
| 182 : | .endfunc | ||
| 183 : | |||
| 184 : | ; sse/sse2 operating support detection routines | ||
| 185 : | ; these will trigger an invalid instruction signal if not supported. | ||
| 186 : | ALIGN 16 | ||
| 187 : | cglobal sse_os_trigger | ||
| 188 : | sse_os_trigger: | ||
| 189 : | xorps xmm0, xmm0 | ||
| 190 : | ret | ||
| 191 : | .endfunc | ||
| 192 : | |||
| 193 : | |||
| 194 : | ALIGN 16 | ||
| 195 : | cglobal sse2_os_trigger | ||
| 196 : | sse2_os_trigger: | ||
| 197 : | xorpd xmm0, xmm0 | ||
| 198 : | ret | ||
| 199 : | .endfunc | ||
| 200 : | |||
| 201 : | |||
| 202 : | ; enter/exit mmx state | ||
| 203 : | ALIGN 16 | ||
| 204 : | cglobal emms_mmx | ||
| 205 : | emms_mmx: | ||
| 206 : | emms | ||
| 207 : | ret | ||
| 208 : | .endfunc | ||
| 209 : | |||
| 210 : | ; faster enter/exit mmx state | ||
| 211 : | ALIGN 16 | ||
| 212 : | cglobal emms_3dn | ||
| 213 : | emms_3dn: | ||
| 214 : | femms | ||
| 215 : | ret | ||
| 216 : | .endfunc | ||
| 217 : | |||
| 218 : |
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