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revision 1.60, Wed Dec 6 19:55:07 2006 UTC revision 1.61, Fri Nov 14 15:43:27 2008 UTC
# Line 171  Line 171 
171  #define XVID_CPU_SSE      (1<< 2) /*       sse : pentium3, athlonXP */  #define XVID_CPU_SSE      (1<< 2) /*       sse : pentium3, athlonXP */
172  #define XVID_CPU_SSE2     (1<< 3) /*      sse2 : pentium4, athlon64 */  #define XVID_CPU_SSE2     (1<< 3) /*      sse2 : pentium4, athlon64 */
173  #define XVID_CPU_SSE3     (1<< 8) /*      sse3 : pentium4, athlon64 */  #define XVID_CPU_SSE3     (1<< 8) /*      sse3 : pentium4, athlon64 */
174    #define XVID_CPU_SSE41    (1<< 9) /*      sse41: penryn */
175  #define XVID_CPU_3DNOW    (1<< 4) /*     3dnow : k6-2 */  #define XVID_CPU_3DNOW    (1<< 4) /*     3dnow : k6-2 */
176  #define XVID_CPU_3DNOWEXT (1<< 5) /* 3dnow-ext : athlon */  #define XVID_CPU_3DNOWEXT (1<< 5) /* 3dnow-ext : athlon */
177  #define XVID_CPU_TSC      (1<< 6) /*       tsc : Pentium */  #define XVID_CPU_TSC      (1<< 6) /*       tsc : Pentium */

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