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revision 1.17.2.30, Sat Feb 15 05:57:15 2003 UTC revision 1.26, Sat Feb 15 18:48:15 2003 UTC
# Line 100  Line 100 
100  #define XVID_CPU_CHKONLY        0x40000000              /* check cpu only; dont init globals */  #define XVID_CPU_CHKONLY        0x40000000              /* check cpu only; dont init globals */
101    
102  #define XVID_CPU_ASM            0x00000080              /* native assembly */  #define XVID_CPU_ASM            0x00000080              /* native assembly */
103  /* ARCH_X86 */  /* ARCH_IS_IA32 */
104  #define XVID_CPU_MMX            0x00000001              /* mmx: pentiumMMX,k6 */  #define XVID_CPU_MMX            0x00000001              /* mmx: pentiumMMX,k6 */
105  #define XVID_CPU_MMXEXT         0x00000002              /* mmxx-ext: pentium2,athlon */  #define XVID_CPU_MMXEXT         0x00000002              /* mmxx-ext: pentium2,athlon */
106  #define XVID_CPU_SSE            0x00000004              /* sse: pentium3,athlonXP */  #define XVID_CPU_SSE            0x00000004              /* sse: pentium3,athlonXP */
# Line 108  Line 108 
108  #define XVID_CPU_3DNOW          0x00000010              /* 3dnow: k6-2 */  #define XVID_CPU_3DNOW          0x00000010              /* 3dnow: k6-2 */
109  #define XVID_CPU_3DNOWEXT       0x00000020              /* 3dnow-ext: athlon */  #define XVID_CPU_3DNOWEXT       0x00000020              /* 3dnow-ext: athlon */
110  #define XVID_CPU_TSC            0x00000040              /* timestamp counter */  #define XVID_CPU_TSC            0x00000040              /* timestamp counter */
111  /* ARCH_IA64 */  /* ARCH_IS_IA64 */
112  #define XVID_CPU_IA64           XVID_CPU_ASM    /* defined for backward compatibility */  #define XVID_CPU_IA64           XVID_CPU_ASM    /* defined for backward compatibility */
113  /* ARCH_PPC */  /* ARCH_IS_PPC */
114  #define XVID_CPU_ALTIVEC        0x00000001              /* altivec */  #define XVID_CPU_ALTIVEC        0x00000001              /* altivec */
115    
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