102 |
#define XVID_CSP_YUY2 (1<< 3) /* 4:2:2 packed */ |
#define XVID_CSP_YUY2 (1<< 3) /* 4:2:2 packed */ |
103 |
#define XVID_CSP_UYVY (1<< 4) /* 4:2:2 packed */ |
#define XVID_CSP_UYVY (1<< 4) /* 4:2:2 packed */ |
104 |
#define XVID_CSP_YVYU (1<< 5) /* 4:2:2 packed */ |
#define XVID_CSP_YVYU (1<< 5) /* 4:2:2 packed */ |
105 |
|
#define XVID_CSP_RGB (1<<16) /* 24-bit rgb packed */ |
106 |
#define XVID_CSP_BGRA (1<< 6) /* 32-bit bgra packed */ |
#define XVID_CSP_BGRA (1<< 6) /* 32-bit bgra packed */ |
107 |
#define XVID_CSP_ABGR (1<< 7) /* 32-bit abgr packed */ |
#define XVID_CSP_ABGR (1<< 7) /* 32-bit abgr packed */ |
108 |
#define XVID_CSP_RGBA (1<< 8) /* 32-bit rgba packed */ |
#define XVID_CSP_RGBA (1<< 8) /* 32-bit rgba packed */ |
170 |
#define XVID_CPU_MMXEXT (1<< 1) /* mmx-ext : pentium2, athlon */ |
#define XVID_CPU_MMXEXT (1<< 1) /* mmx-ext : pentium2, athlon */ |
171 |
#define XVID_CPU_SSE (1<< 2) /* sse : pentium3, athlonXP */ |
#define XVID_CPU_SSE (1<< 2) /* sse : pentium3, athlonXP */ |
172 |
#define XVID_CPU_SSE2 (1<< 3) /* sse2 : pentium4, athlon64 */ |
#define XVID_CPU_SSE2 (1<< 3) /* sse2 : pentium4, athlon64 */ |
173 |
|
#define XVID_CPU_SSE3 (1<< 8) /* sse3 : pentium4, athlon64 */ |
174 |
#define XVID_CPU_3DNOW (1<< 4) /* 3dnow : k6-2 */ |
#define XVID_CPU_3DNOW (1<< 4) /* 3dnow : k6-2 */ |
175 |
#define XVID_CPU_3DNOWEXT (1<< 5) /* 3dnow-ext : athlon */ |
#define XVID_CPU_3DNOWEXT (1<< 5) /* 3dnow-ext : athlon */ |
176 |
#define XVID_CPU_TSC (1<< 6) /* tsc : Pentium */ |
#define XVID_CPU_TSC (1<< 6) /* tsc : Pentium */ |